The invention relates to computer systems, and more particularly to apparatus for arbitrating among a plurality of asynchronous potential master devices contending for access to a computer bus.
The proliferation of microprocessors has produced the economic incentive and consequent trend to construct multimicroprocessor computer systems, where previous implementations used one high-performance processor. There is an attendant need for a bus system through which the microprocessors, and associated data storage modules and peripheral devices can be interconnected. The purpose of any bus structure is to allow devices connected to it to transfer data from one device to another. First, however, the device initiating a data transfer must gain control of the bus. Typically, control will be delegated to any device that requests the bus to establish a communication path between itself and another device connected to the bus. It is possible that two or more devices may attempt to do this at the same ime, i.e., contention may occur. Accordingly, there must be means for deciding which device will first access the bus. The process of making the decision is termed arbitration, and the process is performed by a bus arbitration unit.
A variety of devices may be interconnected by way of a common unitary bus, the devices including processors, data stores and peripheral devices having various operating speeds. In a unitary-bus system, devices other than a central processing unit can gain control of the bus. The device in control of the bus is called a "master", and those devices with which the bus master communicates, are termed "slaves." In a bus protocol such as the Institute of Electrical and Electronic Engineers IEEE 896 Futurebus, each potential master is provided with bus arbitration logic receiving bus access control signals from the master including a unique priority number, and inputs from control lines of the bus indicating activity of other devices connected to the bus including their priority numbers and bus access request signals. The bus arbitration unit, comprising the collective bus arbitration logic in all potential master devices, resolves the bus request contention and assigns the bus to a specific device, permitting that device to become the bus master. Data exchange transactions are established between the bus master and a slave device in a step-by-step manner, utilizing an asynchronous, handshaking process. The master (or slave) device is not permitted to continue dialog with another device until a reply has been received from the slave (or master) device, the timing of each reply being determined by the response characteristics of the devices involved and not by a system clock. Such an asynchronous communication mode allows a system to be technology independent. In a system having abus arbitration controller comprised of logic distributed in the modular devices of the system, it is advantageous to implement the distributed logic inexpensively, in compact microcircuits.
It is an object of the invention to provide an improved bus arbitration controller in a multidevice modular data processing system.
Another object of the invention is to provide an improved bus arbitration controller which is distributed among the controlled devices.
Another object of the invention is to provide new and improved apparatus for implementing a distributed logic bus arbitration controller characterized by inexpensive fabrication of the arbitration units in microcircuit packages.
Another object of the invention is to provide an improved bus arbitration controller which synchronizes the operation of a plurality of asynchronous devices connected to the bus.
Still another object of the invention is to provide an improved bus arbitration controller suitable for use with fault-tolerant systems.